1. Statement of the Technical Field
The invention concerns correlation techniques for use in communications systems and systems for implementing the same. More particularly, the invention concerns an accurate and efficient correlation technique for communications applications, such as synchronizing communications transmitted from transmitters to a receiver, correcting signal transmission delays, and detecting certain channel impairments (such as multipath).
2. Description of the Related Art
In communications systems, correlation techniques are implemented in correlation devices of receivers. The correlation techniques are employed to obtain timing and phase information of a signal being transmitted from a transmitter and a signal being received at a receiver. This timing and phase information is used to correct for transmission time delays, carrier phase offsets occurring in a signal transmission process, and multiple channel paths occurring in a signal transmission process. More particularly, the timing information is used to correct for propagation time delays occurring in transmission paths. The phrase “transmission path” as used herein refers to a path between a transmitter and a receiver of a communications system that a data communications follows. The path can include, but is not limited to, a communications link existing between the transmitter and receiver. The phase information is used to correct carrier phase offsets in the transmission process.
There are many devices known in the art that implement a variety of correlation techniques. One such device is a pipelined correlator such as that shown in FIG. 1. The pipelined correlator is configured to correlate received signals in real time and at a plurality of time delays. In this regard, it should be understood that the pipelined correlator can be comprised of a plurality of delay devices, a plurality of multipliers, and a plurality of adders forming a summer. As shown in FIG. 1, samples of a received signal are communicated to the delay devices. The term “sample” as used herein refers to a quadrature digital value obtained from a continuous signal in a preceeding digital signal processing. The delay devices are configured to delay the samples in time by a pre-determined amount. Stored samples are communicated to the complex multipliers. The stored samples 1, . . . , N can be digital values obtained from a digital signal processing of a received signal or a pseudo-random number sequence.
The multipliers are configured to statically multiply a stored sample 1, . . . , N by a real-time receive signal. In this regard, it should be understood that each multiplier is configured to compute a product utilizing complex multiply arithmetic. For example, a first multiplier is configured to multiply a stored sample N by a time delayed sample SN of a received signal. A second multiplier is configured to multiply a stored sample N−1 by a time delayed sample SN−1, and so on.
The multipliers are also configured to communicate the products of the complex multiply arithmetic to the summer. Upon receipt of the products, the summer adds the same together to obtain a correlation value. If the correlation value magnitude is less than a pre-defined threshold value, then the relative delay is deemed incorrect (i.e., the desired signal is not considered located). If the correlation value magnitude is greater than a pre-defined threshold value, then the relative delay is deemed correct (i.e., the desired signal or correlation peak has been located).
Despite the advantages of this pipelined correlation technique, it suffers from certain drawbacks. For example, this pipelined configuration is a real time process which prevents post-processing verification of the correlation index values. Once the incoming signal passes the ideal correlation peak with the stored or internally generated values, the signal can't be re-correlated. More particularly, the pipelined configuration is absent of dynamic abilities, such as an ability to change samples and an ability to double-check a suspected correlation peak. This pipelined configuration is also hardware intensive and computationally inefficient since all possible values use full length correlations. The expected number of arithmetic operations required to obtain the correlation peak increases linearly with both the uncertainty window and the correlation length. The phrase “uncertainty window” as used herein refers to the bounded temporal range that includes the minimum and maximum possible signal delay. Correlating over the entire uncertainty window is required to be certain of acquiring the signal. This pipelined configuration is further hardware intensive by requiring N dedicated or re-used multipliers. In this regard, it should be appreciated that the pipelined structure can only generate one correlation value per clock cycle. The correlation value represents the sum of all products, where the number of hardware products is the length of the correlation.
In view of the forgoing, there is a need for a method and system implementing an improved efficiency correlation technique. There is also a need in the improved correlation technique to allow for verification of the correlation index values by relaxing the size of the correlation. The improved correlation technique also needs to be less hardware intensive than conventional correlation techniques. The improved correlation technique further needs to be more computationally efficient than conventional correlation techniques.